1. Field of the Invention
The present invention relates to a semiconductor integrate circuit device having a resistance element capable of reducing a dispersion of resistance values among resistance elements.
2. Description of the Related Art
Conventionally, a general semiconductor integrated circuit device of a packaging structure has a silicon chip mounted on a lead frame and molded by a resin. In the semiconductor integrated circuit device, since a silicon chip, lead frame, mount material and molding resin have mutually different thermal expansion coefficients, the silicon chip receives a stress from the lead frame, mount material and molding resin and so forth. Especially after the silicon chip is molded by the resin, the resin contracts in the course of cooling, and thus there arises a compressive stress working from the exterior to the interior of the chip which is as large as in the range of tens to hundreds of MPa.
FIG. 1 is a graph showing a relation of the stress imposed on a chip with the distance from the center of the chip, wherein the stress is represented by a ordinate and the distance is represented by an abscissa. In FIG. 1, a solid line shows a compressive stress and a broken line shows a shearing stress. As shown in FIG. 1, the compressive stress occupies a greater part of the total stress imposed on the chip and has the maximum in the central portion, whereas it is decreased as a measuring point is closer to the periphery of the chip. A changing rate of the compressive stress on the distance is smaller in the central portion but it is drastically enlarged as a measuring point is closer to the periphery of the chip.
On the other hand, as shown by a broken line in the figure, the shearing stress imposed on the chip grows larger as a measuring point is closer to the periphery of the chip. An increment of the shearing stress in the peripheral region offsets the decrease in compressive stress there. As a result, a changing rate of the total stress imposed on the chip on the distance is the smallest in a central region from a line locating at a distance of about one-third of a distance from the center of the chip to the edge thereof. The second smallest of the changing rate is in a peripheral region of the chip with its innermost boundary extending from the same outer edge of the chip to about one-third of a distance from the center of the chip to the outer edge thereof. In the residual region, the changing rate is the maximum.
The stress generating in the interior of the chip is greatly different in magnitude according to a size thereof, a material of a lead frame, an area of an island and a thickness and area of a molding resin.
It is well known that when a stress is externally imposed on a silicon substrate, a change in an average bond distance between silicon atoms affects an energy band structure of silicon, so that an electric conductivity is increased. A resistance value of a diffused resistor formed in a silicon substrate by introducing an impurity therein is changed by a stress generated by an external cause (in general, the resistance value is decreased). This phenomenon is called Piezoresistance Effect.
FIG. 2 is a plan view showing a chip of a conventional semiconductor integrated circuit device. This is hereinafter referred to as the first prior art. As shown in FIG. 2, an array 12 of two resistors each having a rectangular shape parallel to a pair of opposed sides of a chip are arranged in the peripheral region of a substrate 11. An array 13 of two resistors parallel to the array 12 of two resistors is located in a central region with each having a position closer to the center than each of the array 12 of resistors. Functional circuits (not shown) which are connected to the arrays of resistors 12, 13, are formed at the surface of the substrate 11 and thus the chip 14 is constituted.
In the first prior art with such a constitution, the array 13 of resistors has an imposed stress higher on the average than that of the array 12 of resistors and the resistance value is drastically decreased after assembling. Even in the array 13 of resistors, a central portion of the chip 14 is different in decrease of a resistance value from a peripheral portion thereof.
In such a manner, when a resin mold type package is formed, resistance value of a resistance array is different between before and after the package assembling. In a definite manner, a resistance value after the assembling is decreased by about 0 to 10%, compared with a resistance value before the assembling and especially in a portion where the strongest stress is imposed, a resistance value is conspicuously changed.
In order to reduce a influence of Piezo Effect, there have been proposed a various integrated circuit device (see publications of Unexamined Japanese Patent Application No. Sho 57-31167 and Unexamined Japanese Patent Application No. Sho 63-67765). These techniques disclosed in the publications are hereinafter referred to as the second and third prior arts.
FIGS. 3A and 3B are plan views respectively showing configuration of resistance elements according to the second and third prior arts, wherein FIG. 3A shows resistance elements arranged in a peripheral region of a substrate and FIG. 3B shows resistance elements arranged in the vicinity of a corner region of the substrate. As shown in FIGS. 3A and 3B, resistance elements 22, 23, 24 and 25 each extending in a rectangular shape are arranged in regions of a substrate 21. For example, the resistance elements 22, 23, which are required so that a ratio of resistances is always constant, are arranged in parallel to each other. Moreover, in this example, lines which respectively bisect the resistance elements 22, 23 lengthwise both coincide with an arbitrary line Xc perpendicular to an x direction shown in FIG. 3A.
Besides, as shown in FIG. 3B, the resistance elements 24, 25 arranged around the corner of the substrate 21 are also arranged in parallel to each other. Lines bisecting the resistance elements 24, 25 lengthwise both coincide with a diagonal 26 of the substrate 21.
In the chip 27 in which resistance elements are arranged in such a way, since a rate of change in resistance for each resistance element of a pair is equal to the other, resistance ratios between before and after adhering of the chip 27 to a package are equal.
However, since there is a need that lines bisecting two in-parallel arranged resistance elements are coincide with each other in the second prior art, positioning of resistance elements on the substrate 21 is difficult. Especially when each of the pairs of resistance elements 22, 23, 25, 26 are constituted with a plurality more than two of resistance elements, it is difficult to connect between resistance elements respectively belonging to any arbitrary pair, so that a problem arises that a design of elements is complicated.
In the third prior art, resistance elements are arranged in a central region of a chip. In an integrated circuit device constituted in such a way, since resistance elements are arranged in the central region of the chip where a rate of change in stress with a change in distance from the center of the chip is smaller, a dispersion of resistance values in one chip can be resulted in reduction thereof. However, a resistance value itself of a resistance element is subjected to a large change after a chip is adhered to a package, compared with that of the resistance element before the adhesion of the chip.
A resistance element incorporated in, for example, a comparator or the like among those formed in an analogue type IC and the like has a requirement especially for a control of a resistance value with high accuracy. However, if a resistance value after assembling of a package is desired to be controlled with high accuracy, a design for resistance elements has to be made in consideration of a resistance dispersion in a fabrication and such a design is extremely difficult in execution and at the same time increases the number of process steps in the fabrication.
There is available a thin-film resistor as a resistance element with high accuracy in resistance value. However, since the thin-film resistor requires an apparatus and process steps, both special, for formation thereof, it has not widely been popular.
On the other hand, a method wherein a diffused resistor is formed by introducing an impurity in a surface region of a semiconductor substrate is widely used due to simplicity of fabrication thereof and a resistance layer having high accuracy is formed by adopting this diffused resistor. However, there is a limit of .+-.5% for reduction of a dispersion of resistance values of resistors each after the completion of diffusion process when resistance layers are formed with a diffusion resistor. Therefore, in order to control a dispersion of resistance values after the completion of diffusion process steps within a tolerance .+-.5%, there is a need for an assembly process to be carried out in such a manner that a dispersion of resistance values in the assembly process of a package is reduced to be as small as possible.
Since a magnitude of change between before and after the assembly process is different by a different kind of package, it is extremely difficult to estimate a correct magnitude of change in a designing stage. Since an IC such as a gate array generally has a configuration of a plurality of chips of different sizes on an IC substrate, differences in change of resistance value caused by differences in ship size cannot either be neglected. Therefore, to minimize a difference between before and after the assembly process is more required than to reduce dispersion between resistance elements in one chip.